1. Field of the Invention
The present invention relates to solid-state image sensors and imaging systems and particularly, though not exclusively, relates to a solid-state image sensor including a plurality of wiring layers and an imaging system including such a solid-state image sensor.
2. Description of the Related Art
Great improvements due to microfabrication have been made in current amplifier-type solid-state image sensors (hereinafter referred to as CMOS image sensors) manufactured by CMOS technology. In order to enhance properties of such CMOS image sensors, attempts below have been being made.
In a CMOS image sensor, a logic process is usually used causing system heating, which in turn releases thermal photons which trigger a “dark” current in the CMOS sensor. Several conventional methods make a first attempt to reduce the effect of dark currents. A second attempt is to reduce noise, for example, 1/f noise, caused by amplifying circuits including CMOS transistors.
The dark current and the 1/f noise can be reduced by hydrotreating substrates having light-receiving sections arranged thereon. The most effective technique is to heat-treat stacked layers containing a large amount of hydrogen. Examples of such hydrogen-containing layers include silicon nitride layers (plasma SiN layers) formed by a plasma-enhanced CVD process. Such a technique is usually used to manufacture a conventional CCD as discussed in US Patent Application Publication No. 2001/054743 (Japanese Patent Laid-Open No. 10-256518). A hydrotreating process is used to prepare a CMOS image sensor as discussed in US Patent Application Publication No. 2001/023086 (Japanese Patent Laid-Open No. 2001-267547). The use of such a hydrotreating process to prepare CMOS image sensors can cause several problems due to a difference in flatness between interlayer films. Such a difference will now be briefly described.
Conventional CMOS image sensors each include at least two wiring layers. In order to micromachine the wiring layers, a planarization technique, for example, chemical mechanical polishing (CMP), can be used. However, the wiring layers treated by the planarization technique are flat when observed on a microscopic level (several to several tens of micrometers) but are partly nonuniform in thickness when observed on a macroscopic level (several to several tens of millimeters).
The thickness of an interlayer insulating layer polished by the CMP process varies depending on the number of CMOS transistors arranged in a unit area. That is, when the interlayer insulating layer has a peripheral circuit section having the CMOS transistors densely arranged and a pixel section having the CMOS transistors sparsely arranged, the peripheral circuit section has a thickness different from that of the pixel section. The thickness of a third section between these sections gradually varies; hence, the thickness of an effective pixel region also varies. Even if an etchback process is used, a difference in layer thickness is caused because the planar dependency of an apparatus is large.
The following problem is described below in detail: a problem arising from a CMOS image sensor including stacked plasma SiN layers, treated with hydrogen, containing a large amount of hydrogen.
The difference in color between areas can be problematic. That is, when a uniform, bright white surface is monitored, an obtained image has slightly green areas and slightly red areas. This phenomenon is principally caused by the interference between two light beams: a light beam reflected from the interface between a light-receiving face of a substrate and an interlayer insulating layer placed on the light-receiving face and another light beam reflected from the interface between a plasma SiN layer and the interlayer insulating layer. The mechanism of the phenomenon is described below in detail with reference to FIG. 8.
FIG. 8 illustrates a schematic sectional view showing a conventional CMOS image sensor. This CMOS image sensor includes a silicon substrate 701, embedded photodiodes 702 for receiving light, a first interlayer insulating layer 703, a first wiring layer 704, a second interlayer insulating layer 705, a second wiring layer 706, a third interlayer insulating layer 707, a third wiring layer 708, a plasma SiN layer 709 acting as a passivation layer for reducing the dark current, a color filter 710, and microlenses 711, these components being arranged in that order. The silicon substrate 701 has a refractive index of 3.5 to 5.2. The first, second, and third interlayer insulating layers 703, 705, and 707 are made of SiO2 and have a refractive index of 1.4 to 1.5. The plasma SiN layer 709 has a refractive index of 2.0. The color filter 710 has a refractive index of 1.58. The microlenses 711 have a refractive index of 1.58.
In the CMOS image sensor, light is reflected from the interface between the silicon substrate 701 and the first interlayer insulating layer 703 and the interface between the third interlayer insulating layer 707 and the plasma SiN layer 709; hence, a first reflected light beam ref1 and a second reflected light beam ref2 cause interference as shown in FIG. 8. In particular, light beams with a long wavelength cause serious interference, thereby causing serious ripples (interference). If these layers have a uniform thickness, the problem is reduced. However, these layers have a nonuniform thickness when observed on a macroscopic level as described above; hence, the positions of the ripples are shifted. This leads to the occurrence of color inconsistency, thereby causing a further problem.
A cause of this problem is that the plasma SiN layer 709 has a refractive index greater than those of other layers. Another cause of this problem is that the thickness of the first, second, and third interlayer insulating layers 703, 705, and 707 is large, 3 to 5 μm; hence, these layers planarized by CMP have a nonuniform thickness. Thus, the inclusion of SiN passivation layers are not problematic in solid-state image sensors (e.g., CCDs), which include thin interlayer insulating layers that are not planarized. The color inconsistency is a problem for the CMOS image sensor because the first, second, and third interlayer insulating layers 703, 705, and 707 are planarized. This can be explained using the equation 2×L×nsio=kλ, wherein L represents the thickness of an interlayer insulating layer, k represents an integer, and λ represents the resonant wavelength of light. When L is equal to 3.5 μm, λ is 609 or 576 nm if k is equal to 17 or 18, respectively. When L is equal to 1.0 μm, λ is 592 or 493 nm if k is equal to 5 or 6, respectively. Therefore, the ripples are smaller. If the thickness of each interlayer insulating layer is reduced (e.g., from 3.5 to 1.0 μm), the amplitude of the ripples is reduced to about one third because the spectral characteristics of the CMOS image sensor are smoothed.
In order to reduce the above effects, anti-reflective layers that can be used for in-layer lenses for CCDs may be used. U.S. Pat. No. 6,614,479 (Japanese Patent Laid-Open No. 11-103037), which is hereinafter referred to as Patent Document 1, discusses anti-reflective layers. FIG. 9 is an illustration showing a conventional CCD. The CCD includes SiON anti-reflective layers having a refractive index of 1.7 to 1.9 and a SiN layer, placed therebetween, having in-layer lenses; hence, no interface reflecting light is present between the SiN layer and an interlayer insulating layer.
According to this technique, the amount of reflected light can be reduced by 30%. Although the amplitude of ripples is reduced, small ripples appear in short-wavelength regions. A large number of steps are used to prepare a structure including the in-layer lenses discussed in Patent Document 1; hence, the manufacturing cost of a solid-state image sensor having such a structure is high.
US Patent Application Publication No. 2001/054677 (Japanese Patent Laid-Open No. 2001-284566), which is hereinafter referred to as Patent Document 2, discusses a passivation layer having high humidity resistance, high chemical resistance, and barrier properties against metal and impurities (e.g., Na ions and oxygen). The passivation layer is made of SiN, overlies the uppermost wiring layer, and has a refractive index different from that of conventional interlayer insulating layers.
In this configuration, ripples are caused by light rays reflected from the interface between the passivation layer and an interlayer insulating layer and light rays reflected from the surfaces of light-receiving sections. However, Patent Document 2 discusses no technique for solving this problem.
Since the passivation layer has steps, incident light is refracted in an unexpected direction. In order to cope with such a problem, Patent Document 2 discusses another structure including a planarized passivation layer. However, Patent Document 2 discusses no technique for coping with the ripples. Therefore, color inconsistency is an issue in this structure.